The packaging group has finished their design in Allegro Package Designer (APD) and I want to use the etch/conductor delay information from the mcm file in the board design in Allegro PCB Designer. Is there a method to do this?
This can be done by exporting the etch/conductor data from APD and importing it as PIN_DELAY information into Allegro PCB Editor.
If you are generating a length report for use in Allegro Pin Delay, you should consider changing the APD units to Mils and uncheck the Time Delay Report.
In Allegro Package Designer:
- Select File > Export > Board Level Component.
- Select HDL for the Output format and select OK.
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3. Choose a padstack for use when generating the component and select OK.
This will create a file, package_pin_delay.rpt, in the component subdirectory of the current working directory. This file will contain the etch/conductor delay information that can be imported into Allegro.
In Allegro PCB Editor:
- Make sure that the device you want to import delays to is placed in your board design and is visible.
- Select File > Import > Pin delay.
- Browse to the component directory and select package_pin_delay.rpt. The browser defaults to look for *.csv files so you will need to change the Files of type to *.* to select the file.
- You may be prompted with an error message stating that the component cannot be found and you should select one. If so, select the appropriate component.
- Select Import.
- Once the import is completed, select Close.
Note: It is important that all non-trace shapes have a VOLTAGE property so they will not be processed by the the 2D field solver. You should run Reports > Net Delay Report in APD prior to generating the board-level component. This will display the net name of each net as it is processed. If you miss a VOLTAGE property on a net, the net name will show in the report processing window, and you will know which net needs the property.
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