Quantcast
Channel: Cadence IC Packaging and SiP Design Forum
Browsing latest articles
Browse All 218 View Live

Image may be NSFW.
Clik here to view.

What is Allegro X Advanced Package Designer and why do I not see Allegro...

Starting SPB 23.1, Allegro Package Designer Plus (APD+) has been rebranded as Allegro X Advanced Package Designer (Allegro X APD).The splash screen for Allegro X APD will appear as shown below, instead...

View Article


Image may be NSFW.
Clik here to view.

Introducing new 3DX Canvas in Allegro X Advanced Package Designer

Have you heard that starting SPB 23.1, Allegro Package Designer Plus (APD+) will be renamed as Allegro X Advanced Package Designer (Allegro X APD)? Allegro X APD offers multiple new features and...

View Article


Image may be NSFW.
Clik here to view.

How to reuse device files for existing components

Have you ever encountered ERROR(SPMHNI-67) while importing logic? If yes, you might already know that you had to export libraries of the design and make sure that paths (devpath, padpath, and psmpath)...

View Article

Image may be NSFW.
Clik here to view.

How to allow DRCs to the surrounding objects using Etch Back option

Starting from SPB23.1, a new option, Allow DRCs to surrounding metal, has been added in the Etch-Back form to allow DRCs to the surrounding objects. form to allow DRCs to the surrounding objects.The...

View Article

Image may be NSFW.
Clik here to view.

How to add wirebond profile to a die pin?

Starting SPB23.1, a new pin property,WIREBOND_PROFILE_NAME is introduced. This property can be used to define a wirebondprofile to a die pin. When adding a wirebond, the pin will use the profile...

View Article


Image may be NSFW.
Clik here to view.

How to access the Transmission Line Calculator in Allegro X APD

Have you ever thought of a handy utility to specify all necessary transmission line parameters to decide upon the stackup?   Starting SPB 23.1, a handy feature Transmission Line Calculator,is built...

View Article

Image may be NSFW.
Clik here to view.

How to export and import symbols and component properties through Die Text...

Starting SPB 23.1, Allegro X APD lets you import/export the symbol and component properties by using Die Text-In/Out wizards. Exporting the symbol You can export the symbol by using File > Export...

View Article

Image may be NSFW.
Clik here to view.

Skill to delete selected net and padstakck via

Hi,I want to delete via use skill,but i dont write this skill. can you help me.This skill has Interactive interface,the interface can imput  Select Net and select padstack;I can  use temp group to...

View Article


Image may be NSFW.
Clik here to view.

Allegro: Tip of the Week : Push Connectivity

At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net, and it...

View Article


Image may be NSFW.
Clik here to view.

modify bump and export the modified bump

hello, help me!There are many change in the bump design. I want to design bump by APD.The bump(die) is a stagger , create it by die generator. Because,the pin is not isometric. In order to RDL routing,...

View Article

Image may be NSFW.
Clik here to view.

Find Routing problem (Route Vision) and quickly to fix these problems

The vision manager is good tool for routing check. but no quickly or effective  tool to fix or optimize this  problems to be optimized.For example, parallel Gap less than preferred, min seg/Arc...

View Article

Image may be NSFW.
Clik here to view.

DFA check space of compont to BGA ball or BGA PAD in APD

Hi,There are mang components in BGA ball side of flipchip package.Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga  soldermask in allegro APD?I only find space...

View Article

Image may be NSFW.
Clik here to view.

How to avoid adding degassing holes to a particular shape

In a package design, designers often need to perform degassing. This is typically done at the end of the design process before sending the design to the manufacturer.Degassing is a process where you...

View Article


Image may be NSFW.
Clik here to view.

Allegro X APD - Tip of the week: Wondering how to set two adjacent layers as...

By default, a dielectric must separate each pair of conductor layers in the cross-section of a design. In rare cases, this does not represent the real, manufactured substrate.If your design requires...

View Article

Image may be NSFW.
Clik here to view.

slide hug only is wrong?

Hi,Can you tell me which setting is causing this?In the general edit. I try slide via to other position. but the slide is wrong.in the cm,i set pad-pad connect is all allowed,and i turn off via to pad...

View Article


Image may be NSFW.
Clik here to view.

Creating Power and Ground rings in Allegro X Package Designer Plus

Power and Ground rings are exposed rings of metal surrounding a die that supply power/ground to the die and create a low-impedance path for the current flow. These rings ensure stable power...

View Article

Image may be NSFW.
Clik here to view.

Allegro X APD : Tip of the Week: ‘Auto-blank other rats’ feature

When working on a complex design, it is common to have very many net ratlines. Quantities like 1000 ratlines are possible. It can result in a cluttered view while routing. Therefore, it is useful to...

View Article


How to execute APD+ embedded function in my form?

Hello, SKILL experts. I'm studying SKILL language to build some useful function in APD+.Now, I want to execute 'Import Sub-drawing' function in new form.But I cannot find how to do execute APD+...

View Article

Image may be NSFW.
Clik here to view.

Package Design Integrity Checks

When things go wrong with your package design flow, it can sometimes be difficult to understand the cause of the issue. This can be something like a die component is wrongly identified as a BGA, a via...

View Article

Image may be NSFW.
Clik here to view.

Database Maintenance: DBDoctor

The DBDoctor application checks the database for errors and other problems, and presents a report about them. DBDoctor supports .brd, .mcm, .mdd, .psm, .dra, .pad, .sav, and .scf databases.DBDoctor...

View Article

Image may be NSFW.
Clik here to view.

How to transfer etch/conductor delays from Allegro Package Designer (APD) to...

The packaging group has finished their design in Allegro Package Designer (APD) and I want to use the etch/conductor delay information from the mcm file in the board design in Allegro PCB Designer. Is...

View Article


How to make a 3D step copper-filled via on Cadence APD?

I am currently working on a project the requires a 3D step file to perform some electrical simulations. However, when I generate the 3D step file using Cadence APD, the via has no filling/plugging...

View Article


Image may be NSFW.
Clik here to view.

How to delete a Die without removing it from a design entirely

When deleting a symbol in APD, the user receives the following warning message:Deleting Die or BGA instances will result in the deletion of the parent component along with any associated logical...

View Article

Errors in 3D canvas when Via size is less than 100um

I'm using Allegro X APD + 23.1 to create a chiplet package for EM simulation models. I noticed that when the finish size of the drill hole, or the plating size of any layer, is smaller than 100um, they...

View Article

ODB++ Output places components on wrong side

APD designs with flip chip dies on the top and bottom of the board are coming in wrong. Siemens only goes off the 'mirrored' property to determine whether components go on the top or bottom view. So I...

View Article

Browsing latest articles
Browse All 218 View Live