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Allegro tutorials + samples
Hi All, Can anyone suggest me some links for package designing tutorials with some samples to work on that i.e some lab exercises. Thanks in Advance.Originally posted in cdnusers.org by kavitha
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Routing with Cadence SiP 16.01: how to use Virtual pin
Hi everybodyI'd like to add virtual pin in my package design to constraint the length per layer of my Nets. Do someone can help me about?BRAlinOriginally posted in cdnusers.org by razafind
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Of interest: "Chips-in-a-SiP” are a circuit simulation headache"
Of interest to folks in this forum: In the latest “Chip Design” magazine, there is an article titled: “‘Chips-in-a-SiP’” are a circuit simulation headache” Inked by Cadence’s Taranjit Kukal and Keith...
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EDN blogger talks about Allegro 16.2 release
Of interest to readers of this forum. An EDN blogger today talks about our SPB 16.2 release. “Cadence is underlining the observation that no longer can we regard PCB design as somehow a simple...
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Net shielding
Hi everbody I'm a new SI engineer and I'd like to shield nets on my design (package). Does someone can help me to do that? A tutorial would be very interesting. BR Alin
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Single layer boards
Has anyone done anything with single layer flexible cirtuit boards?I am having trouble finding out how to define the cross section for only one layer. The layout cross section window says I can't...
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maximum DC current in wirebond
Hi all,I would like to have an equation of the maximum DC current versus wire size.
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.* file extensions ...
OrCAD PSPICE produces too many important *.* file extensions. Can you please describe or detail the each type file and what for it stands?
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16.2 Cadence Allegro Free Viewer for .mcm's and .sips now available
The 16.2 Allegro Free Viewer has been split into two executables -- one for boards, and one for packages (.mcm/.sip)Both are now available as one install at...
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How to connect top Vss/Vcc net to inner plane segment?
1- Brd cross-section: L1(sig)/L2(Vss)/L3(Vcc)/L4(sig) 2- Set L2 and L3 as negative plane 3- Draw "Shape-> Rectangular" on L2, and assigned net "Vss" successfully 4- Define padstack sucessfully 5-...
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BGA CSP 3D EM tools
HiI just received yesterday "Cadence SiP Layout GXL" for a 1 month evaluation. I did generate a BGA (CSP type for the DIE) and WB but run into trouble with the TH via of a sgle layer BGA. Does anyone...
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Moving Wire Bond in APD16.2 results disconnect Wire and it's Bond Finger
Hi all, I face problem when I want to move the wire bond in APD16.2. After the first nove of the wire bond, when I want to make second time move, the Bond Fingers will shove togather but the wires stay...
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Question about shield
I am new in 16.2, and think constraint driven design is the way to go. I found there is " shield" under CM-properties-Net-general properties-Shield(shield/type). did anyone use this function? does...
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How to change wirebond group in APD16.2? How to use reconnect wire bond in...
Hi all,To change a wirebond group, I select the bondwire and right click>change group> select desired groupin the option panel>done.However, the wire bond group does not change. Pls advice how...
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How to add constraint area in apd16.2?
Hi,In APD15.7, we can add a constraint area by creating a shape and attach the property. However, I have no idea how to create a constraint area in APD16.2. Anyone can help..Thanks,Alice
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BGA Design with a Die Cavity
I am working on a BGA desgin where the die is placed in a cavity. Is there a way to create a cavity in the cross-section in APD 16.2?
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illegal characters of net name
hi, I wanted to create a net with the name contains characters "!"when i input the net name like "VSS!" , it prompts Error Not legal characters.anyone can help on this?thanks in advance
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designlink of Package and PCB
I have finished designlink of Package and PCB.then How to simulate SSN & Voltage ripple by Allegro Pacakge SI ?Can Allegro Package SI do these simulations ?If No, what tool should I use ? such as...
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Weird Layout problem
this post doesn't belong here. It's under Custom IC design now. How do you delete a post anyway? Thanks Emre
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Is there a way to identify this double hits (Via)?
If on the same net DRC, due to the stack via design. Alot of DRC will apply also.Is there a way to identify this issue? Pls advice. Regards,Alice
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