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Setting up Pin Pair in Constraints
Hello Everyone, I was wondering if there was a way to set up the pin pair to multiple net that is connected to same components. For example, a bus group going from IC100 to CN100, but there are other...
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IC-PKG Co-design Webinar Aug 26
There is an excellent IC-Package co-design webinar coming up next week... you may have missed the invitebecause it is posted in the ICD web area.Please see Brad's blog entry for more info and a link...
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same net, 2 constraint values
Hi all,I have a 2 Cline segments of the different width, one is 100 while the other one is 200, they are of the same net (that's say, Net1) and they are connected together.i also have a dynamic shape...
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How to generate Gerber data of bonding wires using APD 16.2
Hi, Is anyone know how to generate gerber data of bonding wires in APD16.2? Pls advise.Thanks,Alice
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How to void shape for same net Bond Finger in APD16.2
Hi all, I have problem to void the shape from the same net bond finger. Although I have set the shape to bond finger spacing, and set the shape parameter to follow DRC rules for Shape Clearence....
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16.3 APD and SiP Free Viewer now available
....in case you did not see it in the PCB forum.http://www.cadence.com/products/pcb/Pages/downloads.aspx Bill
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Standard SIP Export files
Once the SIP design is completed .. I would like to know 1)What Are the files I need to export otherthan solder mask, conductor layers( TOP, layer2, layer3, bottom) and drill file.. ?? 2)How to give...
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Request sucess story of Cadence SiP SI or good case.
Dear SiP MasterThis is Manager of EDA software business.These days, I receive a lot of request from packaging engineers and team manager regarding SiP and SiP SI solution.I can't find a success story...
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Bond pad spacing on diff pairs.....
I'm trying to show shove some bond pads on a path and the diff pairs endup almost touching and don't follow any constraints it seems!Anyone experice this? V16.2 this is... Jim
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How to use "Snap Pick To..." in APD16.2
Hi, There's a function called "Snap Pick To" when I do a move and right click mouse. Is anyonw know how to use it? Will it be the same as the object snap function?Regards,Alice
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Add Via Shape - Package Design
From BGA pin as well from Die bump we will be bringing vias to internal core layers. In the build-up layers there will be lot of same net vias. We would like to add a shape for the multiple vias (same...
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uVia to SMD pin DRC's
We have some UVIA to SMD PIN placement. It is possible that we have some uvia offset by pad center (Die size changes / copy / paste). Is it possible to check / flag DRC’s? FC bump : (-7710.50...
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Shape option in Via Structure
Hi All,Is it possible to enable Shapes option in the Add via structure menu?
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Importing vias in Allegro APD
I want to know how to import via’s into Allegro APD. I have a file that contains the coordinates of my package vias. I want to import them into APD so that I don’t have to manually replace each via. I...
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questions about Allegro Package Designer
hi allI have questions about Allegro Package Designer.1. is it possible to calculate the parasitic R, L, C?2. maximum currents?3. thermal resistance of the body?4. Eatee whether the library of ready...
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Auto Net Assign - Constraint Driven Algorithm
Hi all,I am using APD16.2, and would like to ask about where and how to set the contraint for auto net assign features used.Is the constraint set with cmgr? If it is so, can I add my custom requirement...
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Upcoming Webinar: "Integrated 3D Full-Wave Analysis of Mixed-Signal 3D...
Please excuse the "shameless plug" for an upcoming webinar....http://www.pcbdesign007.com/pages/zone.cgi?a=59596 Bill
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Componet Placement
I cannot place componet on 16.3 but I can on 16.2 on the same design. Is it some setting I need to do? Please help.
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SIP16.3 / How to modify netname
Hello,I have a short question regarding a trouble on SIP netname.on my design i have netname like IO625/LVDS6 , it seems the "/ " is not really appreciate by the system , espacially to do extractions,...
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Monte carlo in TSMC65nm
I am having trouble monte carlo in tsmc65nm. I want to evaluate a delay. The expression I am giving gives same value for all the iterations ( and zero standard deviation). I tried changing ?tran...
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