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Warning message in Cadence SiP Layout XL when importing netlist
Hi,can someone help to solve the problem described bellow?This happens when I try to import a netlist using: File --> Import --> logic --> Others $PACKAGESBGA ! BGA ; BGA WARNING(SPMHNI-152):...
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New to Pspice, can not find IC's..
Dear Sir's, I am new to Pspice and starting reading about this program on the book "Pspice for basic circuit analysis" by: Joseph G. Tront. and downloaded Pspice from Cadence website Ver. 9.1. The...
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QFN in SiP Layout
HiI'm learning cadence sip layout and i have some questions: Where i can get .tcf file? Is it possible to place QFN package in sip layout? thanx in advance
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PROBLEM WITH PLOTING SCHEMATIC TO FILE
I'm trying to plot my schematic to file with cadence 5.1 but when i'm going to do it, i take a message in icfb log which saying: No plotters No size of paper Can anyone help me? PS:I'm sorry for my...
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How to add a wirebond group on APD15.7
Hi! I should be using a bondfinger and via ring on my wirebond lay-out. But I can't seem to do it because when I add a wirebond, the bondfinger is appearing as default and I can't change it to a via...
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Virtuoso XL Layout Question
Hi, I am getting this error; Error: Net "net0160 " (2 bits) can't connect to "MP6 ", pin "D" (32 bits). When I change the MOSFETs back to a single device I have no problems but I am trying to cross...
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Power/Ground Nets
Hello,I'm a newbie in APD and trying to route a flip chip design. I have imported the die information into the design and got the BGA set up. So now, I have the bumps , balls and blind/buried vias...
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PSpice - Creating packages for simulation
Could someone please try to explain/step me through/point me in the right direction on how to use the NAND gates currently available in the PSpice library to create a Quad NAND package? What I'm trying...
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how can i packaging ic
hello i have a monolithic CMOS LSI intelligent chip (Small chip) http://www.aumos.com.tw/ENG/product_pray.html i want to package it in cheapest packaging this ic is 100pin and i will send to you 100...
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Cannot get ODB++ Inside Dialog Box in APD16.3
Hi I am new to ODB++. After install the ODB++ and restart the computer, I still not able to output the correct files from Allegro using ODB++.When I click on Export>ODB++ Inside, it prompts...
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How to generate DIE apart from using DIE text in wizard
Hi Guys, Is there any other way to generate DIE symbol apart from using Die text in wizard? For ex: If we want to create Flip-chip DIE which has got 4000pins, is there any other method instead of using...
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Deleting ball from BGA for APD 16.5
Hi, I previously used APD 15.XX and the balls from BGA could be deleted by going to the 'edit' -> 'BGA' however that option seems to have disappeared in 16.5Can anyone please advise as to how I can...
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DIE/ BGA rotation, before and after generation
Hi, does anyone know how to rotate the die or the bga before and after rotation? Currently working on a stacked die package. Would prefer to know how to do it after generation, but for completeness if...
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Customizing Alias
Hi I am currently using version 16.5 and cannot seem to find the menu to customize the alias (I recall seeing this function) Could someone put me out in the general direction?Thanks in advance!
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SiP Layout 16.5 Algorithm for efficient routing
For N number of pins of a die and M number of pads on the package available, a pin can be connected to a pad in many different ways. Is there a tool or an algorithm that traverses and make the...
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16.3 APD and SiP Free Viewer now available
....in case you did not see it in the PCB forum.http://www.cadence.com/products/pcb/Pages/downloads.aspx Bill
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Set Die Type in Symbol Editor?
We have some Die In custom code that takes a *.die file and runs the APD Die In routine along with other code to generate a die symbol. With newer versions of APD there's a die type parameter on ICs...
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short several nets to power net
Is there a way to short several different net names of power to one main VDD net without having to waive the DRC? Thanks
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checking connectivity
I created an MCM design by creating and placing symbols and importing a netlist. I then used a SKILL routine to import shapes, vias and traces. In principle the design ought to be completely correct...
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