Clik here to view.
create die from a dxf file
Is there a way to create a die from a dxf file with several different die pad sizes? Please help, thanks in advance.
View ArticleClik here to view.
Cadence SiP - stream out - problems converting manufacturing via to GDS
Hi,I'm in the process of writing the layer conversion file (via trial and error) to stream out a SiP design to import to Virtuoso 6.1. When I go to map the via (MANUFACTURING -> NCLEGEND-1-2) it...
View ArticleClik here to view.
Proper routing of trace between bumps (WLCSP or FC design)
Hi, I am routing a trace zigzagging between several Bumps. Somebody suggested that I should keep the traces CENTERED between the bumps so that it is easier to process in etching. But as an effect, the...
View ArticleClik here to view.
Create oblong vent hole with minimum space to signal trace at adjacent layer
HiWith using shape degassing function, anyone knows how to create oblong with minimum spacing to signal trace at adjacent layer. Also, how to set the slot so that it can rotate according to signal...
View ArticleClik here to view.
WARNING(SPMHA1-230)DATABASE HAS NON RECOVERABLE CORRUPTION
hiii,I am using orcad 16.6I am made my new footprint using package wizard . when i used this footprint in my board but i got the error : (SPMHA1-230)DATABASE HAS NON RECOVERABLE CORRUPTION . CONTACT...
View ArticleClik here to view.
PowerSI - Extrapolation difference in Adaptive Frequency Sweep
We are simulating the power impedance of critical power nets using PowerSI. The port impedance is set at 0.1ohm. The frequency sweep used is from 0 to 3GHz, ADAPTIVE SWEEP.In adaptive sweep the result...
View ArticleClik here to view.
About the calculation of resistance and capacitance in a wire.
I have a question that I want to create an wire in layout part in cadence, after DRC check, we can get the resistance and capacitance value. But I can not do that because it is not showing the rules...
View ArticleClik here to view.
Sigrity SystemSI W-element experimentation
Is there a way to save the parameters in the Tline Editor used to generate a W-element? For example, assume you are trying to determine the best stack-up for a substrate design and you want to...
View ArticleClik here to view.
Need advice for product packaging
Hello,I’m new to this forum. I’m Planning to start a small startup from home, Homemade chocolates. I’m looking for a vendor for packaging . What type of packaging should I use clear plastic or pvc...
View ArticleClik here to view.
How to modify default package configuration in APD
Hi,I'm starting a new design in APD (i'm very new to it) and the new package configuration window shows up when I start a new design but it closes right away? not allowing me to select the type of...
View ArticleClik here to view.
Clik here to view.
SiP digital layout lecture manual
Hi,Do anyone here have the full SiP digital layout lecture manual for version 16.2, released on Jan 20, 2009? I am using the manual for v16.6 but I find the manual for v16.2 much easier to...
View ArticleClik here to view.
Shape creation on uvias\pins
Is there a way to create a shape over tangential vias\pins that just covers the edges of the vias\pins? If not, a way to convert clines that connect the uvias\pins to a shape?
View ArticleClik here to view.
PCB Footprint question
Hi,I am trying to design a land pad like the image below... In PADS I used to be able to add all my pins and then a copper area and that would tie all the pins together, there where no errors because...
View ArticleClik here to view.
allegro free viewer 16.6 missing cdnZlib.dll ?
Hello,I had to move from Allegro free viewer 15.7 to 16.6. uninstalled 15.7 and then installed as administrator ( for all users) the 16.6. installation successfully completed. However on startup i got...
View ArticleClik here to view.
Signal Integrity Simulation
Hi folks,I'm new here and need some help and suggestions. I'm trying to learn the PCB Design and SI/PI Analysis tools from Cadence. But get confused because I saw there are a lot of tools related to...
View ArticleClik here to view.
SiP Digital Architect, SiP&PCB parallel developing
Hello All,I am trying to use SiP Digital Architect (System Connectivity Manager) in first time to develop SiP and PCB.I succesfully created SCM project and have ability to transfer changes between SCM...
View ArticleClik here to view.
Help with Encounter terminating with SEGV error
Hello *,I am trying to debug an encounter termination issue at extractRC. I have attached part of the log at the end of this message.I am not sure what is going wrong, this placed design works fine...
View ArticleClik here to view.
Importing .edf files to create .olb file in orcad capture 16.6
Hi all,I'm new to TCL and I tried searching for help on importing .edf files to OrCAD capture 16.6 and creating.OLB files out of it. But I'm not able to find any document or online help. Can anyone...
View ArticleClik here to view.
padframe layout in cadence virtuoso using gpdk180 (0.18um tech.)
I want to make layout of pad / padframe of 40 pin IC in cadence virtuoso using gpdk180 library (0.18um tech.). So which layers are used in making this layout.
View Article