Of interest to folks in this forum: In the latest “Chip Design” magazine, there is an article titled: “‘Chips-in-a-SiP’” are a circuit simulation headache”
Inked by Cadence’s Taranjit Kukal and Keith Felton, the authors describe how today's chip-level circuit simulation environment needs to be able to attach IC package technology to the chip design. Have a read and share your thoughts below.![]()
Inked by Cadence’s Taranjit Kukal and Keith Felton, the authors describe how today's chip-level circuit simulation environment needs to be able to attach IC package technology to the chip design. Have a read and share your thoughts below.